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Project Denver is the codename of a microarchitecture designed by Nvidia that implements the ARMv8-A 64/32-bit instruction sets using a combination of simple hardware decoder and software-based binary translation (dynamic recompilation) where "Denver's binary translation layer runs in software, at a lower level than the operating system, and stores commonly accessed, already optimized code sequences in a 128MB cache stored in main memory". Denver is a very wide in-order superscalar pipeline. Its design makes it suitable for integration with other SIPs cores (e.g. GPU, display controller, DSP, image processor, etc.) into one die constituting a system on a chip (SoC). Project Denver is targeted at mobile computers, personal computers, servers, as well as supercomputers. == Overview == * Pipelined processor with 7-way superscalar execution pipeline * 128 KiB instruction + 64 KiB data L1 cache per core (both 4-way), 2 MiB L2 cache (16-way shared) * Denver also sets aside 128 MiB of main memory as an interpretation cache, which is inaccessible to the main operating system. * Running at up to 2.5 GHz * ARM code is translated either by a hardware translator or through software emulation to an instruction set that is internal to Project Denver. ARM instructions can be reordered, removed if they do not contribute to the end result, or otherwise optimized is used.〔 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「Project Denver」の詳細全文を読む スポンサード リンク
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